1. Field of the Invention
This invention relates in general to the field of memory management in within a computing system, and more particularly to an apparatus and method for extending the kinds of access protections for virtual memory pages beyond those provided for by page protection mechanisms within an existing translation lookaside buffer architecture.
2. Description of the Related Art
Early computing systems executed application programs that were composed especially to run on those systems. The programs consisted of a sequence of instructions that were loaded into the memory of the computing system at the time of execution. Address logic within the computing system generated a memory address each time an instruction was fetched from the memory for execution. Access logic within the computing system placed the memory address out on a memory address bus and the memory provided the contents of the memory location corresponding to the memory address for execution by the computing system. In addition to program instructions, the early computing systems employed memory locations to temporarily store data that was used by application programs. And like the retrieval of program instructions for execution, the storage and retrieval of program data involved the generation of memory addresses that corresponded to data memory locations.
The memory addresses generated by the address logic were directly routed to the early computing systems"" memory busses to access corresponding memory locations. Hence, to access location 10513BC7h in memory required that the address logic generate address 10513BC7h and issue this address to the memory bus. But stated differently, it also is true that when the address logic generated address 10513BC7h, the memory location to which this address corresponded was also location 10513BC7h.
It is intuitive to observe that a direct, one-to-one correspondence between memory addresses generated by a program executing on an early computing system and locations in the computing system""s memory was quickly deemed disadvantageous from many standpoints. First, in order to execute a wide variety of application programs, it was required that the early computing system always provide memory that spanned the full address range of the system. Second, such correspondence unnecessarily coupled the architecture of the computing system to the tools that were used to produce and execute programs on the system. For instance, programs required significant changes to enable the programs to execute on computing systems that exhibited different memory ranges and constraints. And finally, as computers progressed to the point of providing time-share (i.e., multi-tasking) operating systems, performance degradations were observed since all memory management and protection functions had to be performed by the operating systems.
Virtual memory management techniques were developed during the mid-1970""s specifically to address the above-noted problems. In essence, a virtual memory xe2x80x9cmanagerxe2x80x9d within a computing processing unit (CPU) serves as an intermediary between address generation logic in the CPU and access logic that accesses memory locations. Under a virtual memory management scheme, a xe2x80x9cvirtual addressxe2x80x9d generated by the address logic is xe2x80x9ctranslatedxe2x80x9d according to a predefined and configurable mapping strategy into a xe2x80x9cphysical addressxe2x80x9d that is placed on the memory bus to access a corresponding memory location. Hence, virtual memory management overcomes the above-noted limitations of one-to-one correspondence.
Virtual memory management techniques continue to provide benefits that enable the operating system of a computing system to effectively control where application programs are loaded and executed from memory, in addition to providing a means whereby memory can be assigned to a program while it is running and then released back into the memory pool when the memory is no longer required by the program. Most present day virtual memory management units divide a system""s address space into equal-sized chunks called memory pages. To access a memory page requires translation of the upper bits of a virtual address; the lower bits of the virtual address are not translated and merely represent an offset into a page.
Virtual memory management not only applies to the locations associated with memory, but also to the properties, or attributes, associated with those locations. For instance, a virtual page may be designated as read-only so that data writes to locations in the page can be precluded.
The virtual-to-physical address mapping information, along with information specifying the attributes of virtual memory pages, are stored in a designated area of memory known as a page table. Generally speaking, a page table contains one entry for each virtual memory page within the address space of a CPU. Hence, for each memory access, it is required that the page table entry associated with the access be retrieved from the page table so that the virtual address can be translated into a physical address and so that access privileges can be determined.
Translation lookaside buffers (TLBs) have been incorporated into CPU designs to store frequently used page table entries within a CPU so that a memory access is not required each time an address is generated. A TLB is a very fast memory providing storage for a number of page table entries. TLBs are designed to be efficient and fast because they typically lie in the critical timing path of a CPU. Accordingly, only those bits that are essential to the translation of addresses and specification of memory page attributes are provided in a page table entry within a TLB.
TLBs are streamlined to support rapid access for the translation of addresses. As a result, however, the structure of a given TLB is quite static, yielding little or no room for expansion. Hence, if it is desired to update the design of a CPU to incorporate a newly developed or expanded set of memory access protection schemes, then it is highly probable that the design of the CPU""s TLB must be modified to provide for expression of the access restrictions at the virtual page level. But for CPU""s that have relegated a significant portion of their virtual memory management tasks to operating system software, changing the structure of an existing TLB creates incompatibilities with the operating system software-the operating system must be updated in order to provide for memory management according to the new/expanded access restrictions.
A significant market segment is lost, however, when an upgraded CPU becomes no longer compatible with an older operating system and its application programs. CPU manufacturers desire, at least, that CPU upgrades retain compatibility with older software. But compatibility retention in the case of a software managed TLB architecture implies that the number of access privileges that are provided for in a upgraded design be controlled by the existing TLB structure.
Therefore, what is needed is an apparatus that allows extended access protection schemes to be provided via an existing TLB design, where the structure of the TLB is maintained for compatibility with a legacy access protection protocol.
In addition, what is needed is a mechanism for extending the access restrictions of virtual memory pages that utilizes an existing TLB structure.
Furthermore, what is needed is a CPU apparatus that allows more kinds virtual memory page access privileges to be prescribed over that afforded by an existing TLB structure, where the TLB structure also is backwards-compatible with older operating system software.
Moreover, what is needed is a method for extending virtual memory page access protections of an existing TLB, but which defaults to states that can be interpreted according to a legacy access protection protocol.
The present invention provides a superior technique for extending the kinds of access protections afforded to virtual memory pages beyond that provided for by an existing translation lookaside buffer (TLB). The access protections of the virtual memory pages are extended according to the present invention without any detrimental impact on the structure of the TLB or any of the entries therein. The property extensions are provided for by the present invention in such a manner as to allow backwards compatibility with TLB management software in legacy operating systems.
In one embodiment, an apparatus for prescribing extended access restrictions for virtual memory pages is provided. The apparatus includes a translation lookaside buffer (TLB) and extended protection logic. The TLB stores a plurality of TLB entries, where each of the plurality of TLB entries has a flags field and an extended flags field. The extended protection logic is coupled to the TLB. The extended protection logic specifies legacy access restrictions according to the flags field, and specifies the extended access restrictions according to the flags field in combination with the extended flags field. The extended flags field provides further restrictions of the legacy access restrictions indicated by the flags field. Specification of the legacy access restrictions preserves compatibility with a legacy virtual page access protocol.
One aspect of the present invention features a mechanism in a microprocessor for enabling a translation lookaside buffer (TLB) to extend protection schemes of virtual memory pages. The mechanism has a memory management unit for accessing the virtual memory pages. The memory management unit includes TLB entries and extended protection logic. The TLB entries prescribe the protection schemes of the virtual memory pages, where an extended flags field within each of the TLB entries extends protection scheme indications provided for by an existing flags field. The extended protection logic is coupled to the TLB entries. The extended protection logic prescribes a legacy protection scheme according to the existing flags field or an extended protection scheme according to the existing flags field in combination with the extended flags field. The extended flags field provides for further definition of the protection scheme indications provided for by the existing flags field, The legacy protection scheme is backwards-compatible with a legacy virtual page access protocol.
Another aspect of the present invention contemplates a computer program product for use with a computing device. The computer program product includes a computer usable medium, having computer readable program code embodied in the medium. The computer readable program code causes a CPU to be described, the CPU being capable of accessing virtual memory pages according to a legacy protection scheme and an extended protection scheme. The computer readable program code has first program code and second program code. The first program code describes a translation lookaside buffer (TLB), where the TLB is configured to store TLB entries, each entry having an existing flags field and an extended flags field. The second program code describes extended protection logic, where the extended protection logic is configured to specify the legacy protection scheme according to the existing flags field and the extended protection scheme according to the existing flags field in combination with the extended flags field, whereby specification of the legacy protection scheme preserves compatibility with a legacy page access protocol. The extended flags field provides for further restriction of access privileges indicated by the existing flags field.
Yet another aspect of the present invention provides a computer data signal embodied in a transmission medium. The computer data signal includes first computer-readable program code, second computer-readable program code, and third computer-readable program code. The first computer-readable program code describes a translation lookaside buffer (TLB), the TLB being configured to store TLB entries, each of the TLB entries having an existing flags field and an extended flags field. The second computer-readable program code describes extended protection logic, the extended protection logic being configured to specify a legacy protection scheme according to the existing flags field and an extended protection scheme according to the existing flags field in combination with the extended flags field. The extended flags field specifies further restriction of access privileges specified according to the existing flags field. The third computer-readable program code describes access logic, the access logic being configured to access virtual memory pages, where, if a legacy access protocol is employed, the virtual memory pages are accessed in accordance with the legacy protection scheme.
Yet a further aspect of the present invention contemplates a method for accessing a virtual memory page. The method includes reading a first flags field from a translation lookaside buffer (TLB) entry, the first flags field preserving compatibility with a legacy virtual page access protocol by specifying legacy access restrictions in accordance with the protocol; reading a second flags field from the TLB entry, the second flags field in combination with the first flags field specifying extended access restrictions; and further restricting the legacy access restrictions specified by the first flags field according to the second flags field.